Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to an open loop type of a delay locked loop and a method for operating the same.
In general, a semiconductor integrated circuit has been continuously improved to increase an operating speed as well as an integration density. To increase the operating speed of the semiconductor integrated circuit, a synchronous semiconductor integrated circuit designed to operate in synchronization with a source clock provided from the outside of the semiconductor integrated circuit has been developed. Such a synchronous semiconductor integrated circuit employs a closed loop type of a delay locked loop (DLL) which generates an internal clock by delaying a source clock by a certain delay time in order to output data accurately in synchronization with rising and falling edges of the source clock.
The DLL generates an internal clock by compensating a source clock for a delay component inside a semiconductor integrated circuit. This is called a locking operation.
FIG. 1 is a block diagram of a conventional DLL.
Referring to FIG. 1, the conventional DLL 100 includes an input buffer unit 110, a delay line 120, a replica delay 130, a phase comparison unit 140, a delay control unit 150, and an output buffer unit 160. The input buffer unit 110 is configured to buffer a source clock EX_CLK and output an internal clock IN_CLK. The delay line 120 is configured to output an operation clock IN_CLK′ by delaying the internal clock IN_CLK outputted from the input buffer unit 110 in response to a control signal CTR. A replica delay 130 outputs a feedback clock FD_CLK by reflecting/applying a modeled delay amount in/to the operation clock IN_CLK′ outputted from the delay line 120. The modeled delay amount is a delay amount which actually occurs in an input/output data path of the DLL 100. The phase comparison unit 140 is configured to compare a phase of the internal clock IN_CLK outputted from the input buffer unit 110 with a phase of the feedback clock FD_CLK outputted from the replica delay 130. The delay control unit 150 is configured to generate the control signal CTR in response to an output signal of the phase comparison unit 140, and output the control signal CTR to the delay line 120. The output buffer unit 160 is configured to buffer the operation clock IN_CLK′ of the delay line 120 and output a final output signal DLL_CLK. As shown in FIG. 1, the DLL 100 is configured as a closed loop type DLL.
Hereinafter, the operation of the DLL 100 of FIG. 1 is described.
When the source clock EX_CLK is buffered through the input buffer unit 110 and transferred to the delay line 120 as the internal clock IN_CLK, the delay line 120 initially bypasses the internal clock IN_CLK.
In such a state, the operation clock IN_CLK′ of the delay line 120 is fed back to the replica delay 130. The replica delay 130 outputs the feedback clock FD_CLK by delaying the operation clock IN_CLK′ by a delay time corresponding to a modeled delay amount.
The phase comparison unit 140 compares the phase of the internal clock IN_CLK outputted from the input buffer unit 110 with the phase of the feedback clock FD_CLK outputted from the replica delay 130. The delay control unit 150 generates the control signal CTR in response to the output signal of the phase comparison unit 140 and outputs the control signal CTR to the delay line 120.
The delay line 120 outputs the operation clock IN_CLK′ by delaying the internal clock IN_CLK by the corresponding delay time in response to the control signal CTR.
The above-described operations are repeated, and the delay amount of the delay line 120 is locked when the phase of the internal clock IN_CLK is synchronized with the phase of the feedback clock FD_CLK.
Meanwhile, after the delay amount for the delay locking of the delay line 120 is determined, an update operation is performed according to a certain cycle. Jitter factors may be generated in the locked operation clock IN_CLK′ due to noises or the like. To compensate the operation clock IN_CLK′, the above-described delay locking operation is repetitively performed in the update operation.
However, the conventional DLL 100 may have the following concerns.
As described above, since the DLL 100 is to perform the feedback operation several times until the delay locking is achieved, a delay locking time may be lengthened. Furthermore, the long delay locking time increases current consumption.